This invention relates to a three state input circuit and, more particularly, to a three state input circuit constituting an MOS transistor and capable of operating with a low power consumption.
A three state input circuit is constructed to judge three states, namely, states in which an "L" or "H" level input signal is inputted to its input terminal and a state in which the signal input terminal is "open" for producing a 2 bit binary signal. Since the signal input circuit of this type can decrease the number of terminals of a digital circuit device, it is extremely efficient for designing a high density semiconductor integrated circuit.
A three state input circuit having a prior art C-MOS construction is shown in FIG. 1, which comprises a signal input terminal 1, an N channel MOS FET 2, a P channel MOS FET 3, resistors 4, 5, 10 and 11, an input terminal 6 of a first fixed potential source (for example, a positive potential), an input terminal 7 of a second fixed potential source (for example, a ground potential), a first signal output terminal 8, and a second signal output terminal 9.
The signal input terminal 1 is connected to one end of both resistors 10 and 11 and to the gate electrodes of the N channel MOS FET 2 and the P channel MOS FET 3. The other end of the resistor 10 is connected to the input terminal 6 of the first fixed potential source. To the input terminal 6 are also connected the source electrode of the P channel MOS FET 3 and one end of resistor 4, while the other end thereof is connected to the drain electrode of the N channel MOS FET 2, the drain electrode thereof being connected to the second signal output terminal 9. The drain electrode of the P channel MOS FET 3 is connected to the first signal output terminal 8 and to one end of the resistor 5. The other end of this resistor 5 is connected to the input terminal 7 of the second fixed potential source together with the source electrode of the N channel MOS FET 2, and the other end of the resistor 11.
FIG. 2a is a graph showing a threshold potential 14 (for example, 2 V) with reference to the source potential 12 (for example, 5 V) of the N channel MOS FET 2 and the ground potential 13 (for example, 0 V). As shown in FIG. 2a, the path between the source and drain electrodes of the N channel MOS FET 2 becomes conductive when a potential between the threshold potential 14 and the source potential 12 (shown by a shaded area) is applied to its gate electrode; whereas when a potential less than the threshold potential 14 but higher than the ground potential 13 is applied to the gate electrode the source-drain path becomes nonconductive (OFF).
FIG. 2b is a graph showing a threshold potential 15 (for example, 3 V) with reference to the source potential 12 (for example, 5 V) of the P channel MOS FET 3, and the ground potential 13 (for example, 0 V). As shown by FIG. 2b, the source-drain path of the P channel MOS FET 3 becomes conductive when a potential less than the threshold potential 15 and higher than the ground potential 13 (shown by a shaded area) is applied to its gate electrode, whereas becomes nonconductive when a potential higher than the threshold potential 15 but lower than the source potential 12 is applied to the gate electrode.
The operation of a prior art three state input circuit utilizing P channel MOS FET 3 and N channel MOS FET 2 having characteristics as shown in FIGS. 2a and 2b will now be described in the following.
Assume now that +5 V is applied to the first fixed potential source input terminal 6, that 0 V is applied to the second fixed potential source input terminal 7, and that an L level signal 0 V is applied to the signal input terminal 1. Then, since the gate electrodes of both N and P channel MOS FETs 2 and 3 become 0 V, as can be noted from the characteristics shown in FIGS. 2a and 2b, the source-drain path of the N channel MOS FET 2 becomes nonconductive, while the source-drain path of the P channel MOS FET 3 becomes conductive with the result that the drain electrode of the N channel MOS FET 2 becomes an H level and the drain electrode of the P channel MOS FET 3 also becomes an H level because the resistor 5 acts as a pull-down resistor. The H level signals appear at the output terminals 9 and 8, respectively.
Then, when the signal input terminal 1 becomes an open state, a fractional voltage formed by a voltage divider circuit comprising resistors 10 and 11 would be applied to the signal input terminal 1. Where resistors 10 and 11 have substantially the same resistance values (for example, 10 K.OMEGA.-100 K.OMEGA.), the divided voltage would be about 2.5 V, and this voltage is applied to the gate electrodes of the N and P channel MOS FETs 2 and 3, respectively. Then, as can be clearly noted from the characteristics shown in FIGS. 2a and 2b, both P and N channel MOS FETs 3 and 2 become conductive, whereby a potential at an L level of the second fixed potential source appears at the drain electrode of the N channel MOS FET 2 and a potential at an H level of the first fixed potential source appears at the drain electrode of the P channel MOS FET 3. These L and H level signals are outputted through the second and the first signal output terminals 9 and 8, respectively.
Upon application of an H level signal (5 V) on the signal input terminal 1, the gate electrodes of the N and P channel MOS FETs 2 and 3 become the H level (5 V), so that as can be noted from the characteristics shown in FIGS. 2a and 2b, the source-drain path of the N channel MOS FET 2 becomes conductive, while the source-drain path of the P channel MOS FET 3 becomes nonconductive. As a consequence, the drain electrode of the N channel MOS FET 2 would be connected to the second fixed potential source to assume the L level. At the same time, the drain electrode of the P channel MOS FET 3 is connected to the second fixed potential source via resistor 5 so that it also becomes the L level and these L level signals are outputted through the second and first signal output terminals 9 and 8.
The input and output relationships described above can be summarized as shown in the following Table I.
TABLE I ______________________________________ First signal Second signal Input level output terminal output terminal ______________________________________ H L L open H L L H H ______________________________________
As this table clearly shows the H, open and L level signals inputted to the signal input terminal 1 are decoded into 2 bit binary signals and then outputted.
Above described prior art three state input circuit, however, has the following defects.
(1) Irrespective of the state of the signal input terminal 1, a current always flows through the input circuit so that such input circuit cannot be used for a circuit device consuming low electric power. For example, when the first fixed potential source terminal 6 is at a potential of 6-16 V, a current of several hundred microamperes flows.
(2) For the purpose of decreasing the number of the component parts, resistors 10 and 11 constituting a voltage divider are formed by diffusing a resistive material into the surface of a semiconductor substrate. Actually, however, the values of these resistors do not deviate in the same direction from respective designed values. This causes the divided voltage to vary so that it is difficult to obtain a bias potential for simultaneously turning ON both P and N channel MOS FETs 3 and 2.
(3) As the threshold voltages V.sub.T of the P and N channel MOS FETs 3 and 2 vary depending upon the conditions during manufacturing, it is difficult to correctly match the threshold voltages V.sub.T with the design values. More particularly, the conduction regions of the P channel MOS FET 3 and the N channel MOS FET 2 tend to become narrow, whereby the threshold voltages V.sub.T of the MOS FETs 2 and 3 approach each other. Accordingly, the range in which a judgement is made as to whether the signal input terminal 1 is in an open state or not is restricted, thus causing erroneous operations. Especially, in the prior art circuit it is almost impossible to operate the input circuit with a source voltage of less than 5 V.